View PT6314-16_1788101.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 1 - march, 2006 dot character vfd controller/driver ic pt6314 description pt6314 is a vfd controller/driver ic utilizing cmos technology providi ng 80 segment outputs and 24 grid outputs. it supports dot matrix displays of up to 16 columns x 2 lines, 20 columns x 2 lines or 24 columns x 2 lines. pt6314 also features a charac ter generator rom which stores 240 x 5 x 8 dos characters. pin assignments and application circui ts are optimized for easy pcb layout and cost saving advantages. features ? cmos technology ? provides up to 80 x 8 display ram ? capable of driving segment for cursor displays (48 units) ? built-in oscillation circuit ? parallel data input/output (switchable 4 or 8 bits) or serial data input/output ? alphanumeric and symbolic display via the bui lt-in rom (5 x 8 dots): 240 characters ? eight user-defined 5 x 8 dot character cgram ? display contents capability: - 16 columns x 2(1) rows + 32(16) cursors - 20 columns x 2(1) rows + 40(20) cursors - 24 columns x 2(1) rows + 48(24) cursors ? custom rom available (please contact ptc) applications ? electronic equipment with vfd display ? microprocessor peripherals
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 2 - march, 2006 dot character vfd controller/driver ic pt6314 block diagram oscillation circuit osc1 sg1 sg2 sg3 sg4 sg5 sg6 sg7 sg 7 9 sg8 sg80 testout ifsel rs/stb e(/rd)/sck test /cs r/w(/wr) si/so db0 db5 db1 db2 db7 /reset mpu ds1 ds0 rl1 dls db3 db4 osc2 sdo clk vdd1 vdd2 vss1 vss2 slk / clr latch gr1 gr10 gr2 gr11 gr3 gr12 gr4 gr5 gr6 gr7 gr22 gr8 gr2 3 gr9 gr24 i/o buffer instruction register data register instruction decoder timing generator 24 bits shift register grid signal driver 8 8 7 8 8 8 8 8 55 7 address counter 7 7 7 24 24 character generator ram (cgram) 8x5x8 bits character generator rom (cgrom) 248x5x8 bits parallel to serial data converter cursor blink control circuit display data ram (ddram) 80x8 bits 80 bits shift register 80 bits latch segment signal driver 80 80 reset circuit
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 3 - march, 2006 dot character vfd controller/driver ic pt6314 pin configuration vdd2 nc 1 108 2 107 3 106 4 105 5 104 6 103 7 102 8 101 9 100 10 99 11 98 12 13 96 14 95 15 94 16 93 17 92 18 91 19 90 20 89 21 88 22 87 23 86 24 85 25 84 26 83 27 82 28 81 29 80 30 79 31 78 32 77 33 76 34 75 35 74 36 73 vss2 vdd1 clk osc2 osc1 reset test dls ds1 ds0 r/w rs/stb e/sck s1/s0 db0 db1 db2 db3 db4 db5 db6 db7 ifsel mpu /cs rl1 rl2 clr latch sdo slk testout vss1 vss2 vdd2 nc nc nc nc 38 143 39 40 141 41 140 42 139 43 138 44 137 45 136 46 135 47 134 48 133 49 132 50 131 51 130 52 129 53 128 54 127 55 126 56 125 57 124 58 123 59 122 60 121 61 120 62 119 63 118 64 117 65 116 66 115 67 114 68 113 69 112 70 111 71 110 72 109 37 97 144 142 pt6314 note: pin no. 38 to 71, 73 to 108, 110 to 119 are used as segment signal output pins, pin no.120 to 143 are used as grid signal output pins and are configured a ccording to the tables shown in the duty ratio setting section (see pages 7 to 13).
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 4 - march, 2006 dot character vfd controller/driver ic pt6314 pin description pin name i/o description pin no. vdd2 - vfd driving power supply pin 1, 36 vss2 - vfd driving power supply pin 2, 35 vdd1 - logic power supply pin 3 osco o oscillation signal output pin 4 osc2 o oscillation output pin 5 osc1 i oscillation input pin 6 /reset i reset pin when this pin is set to ?0?, all internal registers and commands are initialized. the segment and grid outputs are fixed to vdd. 7 test i test pin 0 or floating : the normal operation mode 1:the test mode is active 8 dls i display line select pin this pin is used to select the number of display lines when the power is on, reset or resetting. 0: 1 line is selected (n=?0?)* 1: 2 lines are selected (n=?1?)* 9 ds1, ds0 i duty select pin these pins set the duty ratio. the duty ratio is determined by the number of grid. 10, 11 r/w(/wr) i read/write (write) signal pin under the m68 parallel data transfer mode (r/w), this pin functions as the data transfer select pin. 0: write function 1: read function under the i80 parallel data transfer mode (/wr), this pin is write enable pin. it writes data at the rising edge of this signal. under the serial transfer mode, the read or write function is selected by instruction and this pin is connect to either ?h? or ?l?. 12 rs/stb i register select/strobe pin under the parallel transfer mode is selected, this pin acts as the register select pin. 0:instruction register (ir) 1: data register (dr) under serial data transfer mode, this pin acts as the strobe input pin. 13 e(/rd)/sck i enable (read)/shift clock under the m68 parallel data transfer mode (e), this pin functions as the write enable pin. data is written at the falling edge. under the i80 parallel data transfer mode (/rd), this pin functions as the read enable pin. when this pin is set to ?low?, data is outputted to the data bus. under the serial data transfer mode, this pin functions as the shift clock input pin. data is written at the rising edge. 14 note: *=n is the display line select flag in ?function set? command
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 5 - march, 2006 dot character vfd controller/driver ic pt6314 pin name i/o description pin no. si/so i/o serial input/output pin under the serial data transfer mode, this pin functions as an i/o pin. under the parallel data transfe r mode, this pin may be connected to either ?h? or ?l? 15 db0 to db7 i/o parallel data input/output pins under the parallel data transfer mode, these pins are used as i/o pin. under the 4-bit transfer mode, db4 to db7 are used. 16-23 ifsel i i/f select pin this pin is used to select the i/f mode: serial or parallel transfer 0: serial data transfer 1: parallel data transfer 24 mcu i interface select pin this pin is used to select the interface mode: i80 or m68. 0: i80 cpu mode 1: m68 cpu mode 25 /cs i chip select pin when this pin is set to ?l? the pt6314 is active. 26 rl1,rl2 i segment output select pin this pins are used to set sg1 to sg80. 27, 28 /clr o extension grid driver clear signal output pin active: low the grid data stored in extens ion driver latch are outputted when this pin is set to ?high?. if this pin is set to ?low?, the extension driver outputs low. 29 latch o extension grid driver latch enable signal output pin 30 sdo o extension grid driver serial data output pin 31 slk o extension grid driver shift clock output pin rising edge: active 32 testout o test pin for ic testing only. this pin should be ?open?. 33 vss1 - logic ground pin 34 gr1 to gr24 o grid signal output pins 143-120 sg1 to sg80 o segment signal output pins see (1) note: refer to duty ratio setting section
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 6 - march, 2006 dot character vfd controller/driver ic pt6314 duty ratio setting ds0 and ds1 control the duty ratio of pt6314. please refer to the table below. ds0 ds1 duty ratio 0 0 1/16 (no. of grid=16) 0 1 1/24 (no. of grid=24) 1 0 1/20 (no. of grid=20) 1 1 1/40 ( no. of grid=40) please take note that the external extension grid driver is needed to set up 1/40 duty mode. segment setting condition 1: 2-line display (n=?1?), rl1=?0? and rl2=?0? the number of segment pins is controlled by the rl1 and rl2. pin name pin no. pin name pin no. pin name pin no. pin name pin no. sg1 38 sg18 55 nc 72 sg51 89 sg2 39 sg19 56 sg35 73 sg52 90 sg3 40 sg20 57 sg36 74 sg53 91 sg4 41 sg21 58 sg37 75 sg54 92 sg5 42 sg22 59 sg38 76 sg55 93 sg6 43 sg23 60 sg39 77 sg56 94 sg7 44 sg24 61 sg40 78 sg57 95 sg8 45 sg25 62 sg41 79 sg58 96 sg9 46 sg26 63 sg42 80 sg59 97 sg10 47 sg27 64 sg43 81 sg60 98 sg11 48 sg28 65 sg44 82 sg61 99 sg12 49 sg29 66 sg45 83 sg62 100 sg13 50 sg30 67 sg46 84 sg63 101 sg14 51 sg31 68 sg47 85 sg64 102 sg15 52 sg32 69 sg48 86 sg65 103 sg16 53 sg33 70 sg49 87 sg66 104 sg17 54 sg34 71 sg50 88 sg67 105 sg68 106 sg77 116 gr18 126 gr8 136 sg69 107 sg78 117 gr17 127 gr7 137 sg70 108 sg79 118 gr16 128 gr6 138 nc 109 sg80 119 gr15 129 gr5 139 sg71 110 gr24 120 gr14 130 gr4 140 sg72 111 gr23 121 gr13 131 gr3 141 sg73 112 gr22 122 gr12 132 gr2 142 sg74 113 gr21 123 gr11 133 gr1 143 sg75 114 gr20 124 gr10 134 nc 144 sg76 115 gr19 125 gr9 135
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 7 - march, 2006 dot character vfd controller/driver ic pt6314 condition 2: 2-line display (n=?1?), rl1=?0?, rl2=?1? pin name pin no. pin name pin no. pin name pin no. pin name pin no. sg40 38 sg23 55 nc 72 sg51 89 sg39 39 sg22 56 sg6 73 sg52 90 sg38 40 sg21 57 sg5 74 sg53 91 sg37 41 sg20 58 sg4 75 sg54 92 sg36 42 sg19 59 sg3 76 sg55 93 sg35 43 sg18 60 sg2 77 sg56 94 sg34 44 sg17 61 sg1 78 sg57 95 sg33 45 sg16 62 sg41 79 sg58 96 sg32 46 sg15 63 sg42 80 sg59 97 sg31 47 sg14 64 sg43 81 sg60 98 sg30 48 sg13 65 sg44 82 sg61 99 sg29 49 sg12 66 sg45 83 sg62 100 sg28 50 s g11 67 sg46 84 sg63 101 sg27 51 sg10 68 sg47 85 sg64 102 sg26 52 sg9 69 sg48 86 sg65 103 sg25 53 sg8 70 sg49 87 sg66 104 sg24 54 sg7 71 sg50 88 sg67 105 sg68 106 sg77 116 gr18 126 gr8 136 sg69 107 sg78 117 gr17 127 gr7 137 sg70 108 sg79 118 gr16 128 gr6 138 nc 109 sg80 119 gr15 129 gr5 139 sg71 110 gr24 120 gr14 130 gr4 140 sg72 111 gr23 121 gr13 131 gr3 141 sg73 112 gr22 122 gr12 132 gr2 142 sg74 113 gr21 123 gr11 133 gr1 143 sg75 114 gr20 124 gr10 134 nc 144 sg76 115 gr19 125 gr9 135
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 8 - march, 2006 dot character vfd controller/driver ic pt6314 condition 3: 2-line display (n=?1?), rl1=?1?, and rl2=?0? pin name pin no. pin name pin no. pin name pin no. pin name pin no. sg41 38 sg58 55 nc 72 sg30 89 sg42 39 sg59 56 sg75 73 sg29 90 sg43 40 sg60 57 sg76 74 sg28 91 sg44 41 sg61 58 sg77 75 sg27 92 sg45 42 sg62 59 sg78 76 sg26 93 sg46 43 sg63 60 sg79 77 sg25 94 sg47 44 sg64 61 sg80 78 sg24 95 sg48 45 sg65 62 sg40 79 sg23 96 sg49 46 sg66 63 sg39 80 sg22 97 sg50 47 sg67 64 sg38 81 sg21 98 sg51 48 sg68 65 sg37 82 sg20 99 sg52 49 sg69 66 sg36 83 sg19 100 sg53 50 sg70 67 sg35 84 sg18 101 sg54 51 sg71 68 sg34 85 sg17 102 sg55 52 sg72 69 sg33 86 sg16 103 sg56 53 sg73 70 sg32 87 sg15 104 sg57 54 sg74 71 sg31 88 sg14 105 sg13 106 sg4 116 gr18 126 gr8 136 sg12 107 sg3 117 gr17 127 gr7 137 sg11 108 sg2 118 gr16 128 gr6 138 nc 109 sg1 119 gr15 129 gr5 139 sg10 110 gr24 120 gr14 130 gr4 140 sg9 111 gr23 121 gr13 131 gr3 141 sg9 112 gr22 122 gr12 132 gr2 142 sg7 113 gr21 123 gr11 133 gr1 143 sg6 114 gr20 124 gr10 134 nc 144 sg5 115 gr19 125 gr9 135
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 9 - march, 2006 dot character vfd controller/driver ic pt6314 condition 4: 2-line display (n=?1?), rl1=?1? and rl2=?1? pin name pin no. pin name pin no. pin name pin no. pin name pin no. sg80 38 sg63 55 nc 72 sg30 89 sg79 39 sg62 56 sg75 73 sg29 90 sg78 40 sg61 57 sg76 74 sg28 91 sg77 41 sg60 58 sg77 75 sg27 92 sg76 42 sg59 59 sg78 76 sg26 93 sg75 43 sg58 60 sg79 77 sg25 94 sg74 44 sg57 61 sg80 78 sg24 95 sg73 45 sg56 62 sg40 79 sg23 96 sg72 46 sg55 63 sg39 80 sg22 97 sg71 47 sg54 64 sg38 81 sg21 98 sg70 48 sg53 65 sg37 82 sg20 99 sg69 49 sg52 66 sg36 83 sg19 100 sg68 50 sg51 67 sg35 84 sg18 101 sg67 51 sg50 68 sg34 85 sg17 102 sg66 52 sg49 69 sg33 86 sg16 103 sg65 53 sg48 70 sg32 87 sg15 104 sg64 54 sg47 71 sg31 88 sg14 105 sg13 106 sg4 116 gr18 126 gr8 136 sg12 107 sg3 117 gr17 127 gr7 137 sg11 108 sg2 118 gr16 128 gr6 138 nc 109 sg1 119 gr15 129 gr5 139 sg10 110 gr24 120 gr14 130 gr4 140 sg9 111 gr23 121 gr13 131 gr3 141 sg9 112 gr22 122 gr12 132 gr2 142 sg7 113 gr21 123 gr11 133 gr1 143 sg6 114 gr20 124 gr10 134 nc 144 sg5 115 gr19 125 gr9 135
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 10 - march, 2006 dot character vfd controller/driver ic pt6314 condition 5:1-line display (n=?0?), rl2=?0? the rl1 setting is irrelevant. the table below shows the segment pin setting. pin name pin no. pin name pin no. pin name pin no. pin name pin no. sg1 38 sg18 55 nc 72 * 89 sg2 39 sg19 56 sg35 73 * 90 sg3 40 sg20 57 sg36 74 * 91 sg4 41 sg21 58 sg37 75 * 92 sg5 42 sg22 59 sg38 76 * 93 sg6 43 sg23 60 sg39 77 * 94 sg7 44 sg24 61 sg40 78 * 95 sg8 45 sg25 62 * 79 * 96 sg9 46 sg26 63 * 80 * 97 sg10 47 sg27 64 * 81 * 98 sg11 48 sg28 65 * 82 * 99 sg12 49 sg29 66 * 83 * 100 sg13 50 s g30 67 * 84 * 101 sg14 51 sg31 68 * 85 * 102 sg15 52 sg32 69 * 86 * 103 sg16 53 sg33 70 * 87 * 104 sg17 54 sg34 71 * 88 * 105 * 106 * 116 gr18 126 gr8 136 * 107 * 117 gr17 127 gr7 137 * 108 * 118 gr16 128 gr6 138 nc 109 * 119 gr15 129 gr5 139 * 110 gr24 120 gr14 130 gr4 140 * 111 gr23 121 gr13 131 gr3 141 * 112 gr22 122 gr12 132 gr2 142 * 113 gr21 123 gr11 133 gr1 143 * 114 gr20 124 gr10 134 nc 144 * 115 gr19 125 gr9 135 note: *=not used
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 11 - march, 2006 dot character vfd controller/driver ic pt6314 condition 6: 1-line display, rl2=?1? the rl1 setting is irrelevant. segment output pin settings are as follows: pin name pin no. pin name pin no. pin name pin no. pin name pin no. sg40 38 sg23 55 nc 72 * 89 sg39 39 sg22 56 sg6 73 * 90 sg38 40 sg21 57 sg5 74 * 91 sg37 41 sg20 58 sg4 75 * 92 sg36 42 sg19 59 sg3 76 * 93 sg35 43 sg18 60 sg2 77 * 94 sg34 44 sg17 61 sg1 78 * 95 sg33 45 sg16 62 * 79 * 96 sg32 46 sg15 63 * 80 * 97 sg31 47 sg14 64 * 81 * 98 sg30 48 sg13 65 * 82 * 99 sg29 49 sg12 66 * 83 * 100 sg28 50 s g11 67 * 84 * 101 sg27 51 sg10 68 * 85 * 102 sg26 52 sg9 69 * 86 * 103 sg25 53 sg8 70 * 87 * 104 sg24 54 sg7 71 * 88 * 105 * 106 * 116 gr18 126 gr8 136 * 107 * 117 gr17 127 gr7 137 * 108 * 118 gr16 128 gr6 138 nc 109 * 119 gr15 129 gr5 139 * 110 gr24 120 gr14 130 gr4 140 * 111 gr23 121 gr13 131 gr3 141 * 112 gr22 122 gr12 132 gr2 142 * 113 gr21 123 gr11 133 gr1 143 * 114 gr20 124 gr10 134 nc 144 * 115 gr19 125 gr9 135 note: *=not used
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 12 - march, 2006 dot character vfd controller/driver ic pt6314 vfd display pt6314 supports 24 character x 2 display lines. please refer to the diagram below for vfd display construction. sg40 sg41 sg80 gr1 gr2 gr24 sg1 sg1 sg71 sg5 sg75 sg6 sg76 sg10 sg80
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 13 - march, 2006 dot character vfd controller/driver ic pt6314 function description block functions cpu interface pt6314 provides either 4 or 8 bits parallel or serial interface. t hese interface modes may be selected using the ifsel pin (pin no.24) as follows: ifsel setting data transfer mode ?0? serial data transfer ?1? parallel data transfer registers (instruction register & data register) pt6314 supports two 8-bit registers, namely: an instru ction register (ir) and a data register (dr) which may be selected using the register select or (rs) signal. please refer to table below. ifsel /cs rs e/sck r/w mcu si/so dbn 0 /cs stb sck * * si/so * 1 /cs rs e/(/rd) r/d(/wr) mcu * dbn note: *=this pin must be kept in either ?high? or ?low? state. the instruction register (ir) stores (1) instruction codes (i.e. display clear and cursor shift), (2) display data ram (ddram) address information and (3) c haracter generator ram (cgram). it can only be written from the mcu. the data register (dr) acts as a temporary st orage for (1) data to be written into the ddram or cgram and (2) data to be read from the ddram or cgram. data wri tten into the dr from the mcu is automatically written into t he ddram or cgram by internal oper ation. when the data stored in dr is read by the mcu, data transfer is completed. afte r the completion of the data transfer (that is, after the mcu has finished reading the first set of data) , the ddram or cgram data in the next address is sent to the dr. the mcu then again performs it s read operation for the next set of data.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 14 - march, 2006 dot character vfd controller/driver ic pt6314 busy flag (read bf flag) the busy flag data (db7) always outputs ?0?. address counter (ac) the address counter (ac) designates the addr esses of the ddram and cgram. when an address of instruction is written into the instruction register, the address inform ation is sent from the instruction register (ir) to the address counter. the selecti on of either the dram or cgram is also determined concurrently by the instruction. after writing into the ddram or cgram, the address counter is increased by 1. (the address counter is decreas ed by 1 after data is read from the ddram or cgram.) the contents of the address counter ar e then outputted to the db0~db6 when rs=?0? and r/w=?1?. please refer to the table below. common m68 i80 rs r/w /rd /wr register selection 0 0 1 0 write ir data as internal operation (i.e. display clear) 0 1 0 1 read data to busy flag (db7) and address counter (db6 to db0) 1 0 1 0 write dr data (dr ddram/cgram) 1 1 0 1 read dr data (ddram/cgram dr)
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 15 - march, 2006 dot character vfd controller/driver ic pt6314 display data ram (ddram) the display data ram (ddram) stores the displa y data shown in the 8-bit character codes. when expanded the display data ram supports a capacity of 80 x 8 bits or 80 characters. the area in the ddram that is not in used for display may be used as general data ram. high order bits low order bits ac ac6 ac5 ac4 ac3 ac2 ac1 ac0 hexadecimal hexadecimal please note that the ddram address (add) is se t in the address counter(ac) as hexadecimal. example: ddram address ?26?: 0 1 0 0 1 1 0 2 6 n=?0? 1-line display, 80 characters display position digit 1 2 3 4 5 6 ?? 79 80 ddram address(hexadecimal) 00 01 02 03 04 05 ?? 4e 4f n=?0? 1-line display, less than 80 characters in cases when there are less than 80 display charac ters, the display begins at the head position. for example, if only one piece of pt6314 is being used, 24 characters are displayed. when the display shift operation is performed, the ddram address shifts, please refer to the figure below. display position digit 1 2 3 4 5 6 ?? 23 24 ddram address(hexadecimal) 00 01 02 03 04 05 ?? 16 17 for shift-left 01 02 03 04 05 06 ?? 17 18 for shift-right 4f 00 01 02 03 04 ?? 15 16 n=?1? 2-line display, 40 characters display position digit 1 2 3 4 5 6 ?? 39 40 00 01 02 03 04 05 ?? 26 27 ddram address (hexadecimal) 40 41 42 43 44 45 ?? 66 67
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 16 - march, 2006 dot character vfd controller/driver ic pt6314 n=?1? 2-line display, less than 40 characters in cases when the number of display characters is less than 40 x 2 lines, the two lines are displayed from the head. the line end address and the second line start address are not consecutive. for example, if only one pt6314 is being used, 24 characte rs x 2 lines are displayed. when the display shift operation is performed, the ddram address shifts. display position digit 1 2 3 4 5 6 ?? 23 24 00 01 02 03 04 05 ?? 16 17 ddram address (hexadecimal) 40 41 42 43 44 45 ?? 56 57 01 02 03 04 05 06 ?? 17 18 for shift-left 41 42 43 44 45 46 ?? 57 58 27 00 01 02 03 04 ?? 15 16 for shift-right 67 40 41 42 43 44 ?? 55 56 n=?1?:2-line display, 40 characters pt6314 can be extended using one of the 16 output extens ion drivers as grid. under this condition, a 40-character x 2 lines display may be constructed. display position digit 1 2 3 4 ?? 23 24 25 ?? 39 40 00 01 02 03 ?? 16 17 18 ?? 26 27 ddram address (hexadecimal) 40 41 42 43 ?? 56 57 58 ?? 66 67 digit 1 2 3 4 ?? 23 24 25 ?? 39 40 01 02 03 04 ?? 17 18 19 ?? 27 00 for shift-left 41 42 43 44 ?? 57 58 59 ?? 67 40 digit 1 2 3 4 ?? 23 24 25 ?? 39 40 27 00 01 02 ?? 15 16 17 ?? 25 26 for shift-right 67 40 41 42 ?? 55 56 57 ?? 65 66 pt6314 display extension driver display
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 17 - march, 2006 dot character vfd controller/driver ic pt6314 character generator rom (cgrom) the cgrom is the read only memory (rom) responsible for the generation of 5 x 8 dots character patterns from 8-bit character codes. a total of up to 240 character patterns can be generated. please note that character codes -- 00h to 0fh are allocated to the cgram. character generator ram (cgram) the character generator ram (cgram) allows the us er to reconstruct the character patterns from 8-bit by software programming. eight character pa tterns can be written and constructed using 5 x 8 dots. areas that are not used for displa y purposes may be used as general data ram. the table below shows the relationship between the cgram address, character code (ddram) and the 5x7 (cursor included) dot character patterns (cgram). character code (ddram data) cgram address cgram data d7 d6 d5 d4 d3 d2 d1 d0 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 high order bit low order bit high order bit low order bit high order bit low order bit 0 0 0 0 x 0 0 0 0 0 0 0 0 0 x x x 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 character pattern no. 1 1 1 1 0 0 0 0 0 cursor position 0 0 0 0 x 0 0 1 0 0 1 0 0 0 x x x 1 1 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 character pattern no. 2 1 1 1 0 0 0 0 0 cursor position 0 0 0 0 x 1 1 1 1 1 1 0 0 0 x x x 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 character pattern no. 8 1 1 1 1 1 1 1 1 cursor position notes: 1. x= irrelevant 2. character code bits 0 to 2 correspond to the cgram address bits 3 to 5 (3 bits: 8 type). 3. cgram address bits 0 to 2 deter mine the character pattern line positi on. the 8th line is the cursor position and its display is formed by a logical or with the cursor. maintain the 8th line data, corresponding to the cursor display position at 0 as the cursor display. if the 8th line data is ?1? all the 1 bits will light up the 8th line regardless of the cursor presence. 4. character pattern row position corresponds to the cg ram data bits 0 to 4. (bit 4 is positioned at the left) 5. the cgram character patterns are selected when the character code bits 4 to 7 are all set to ?0?. the character code bit 3 is irrelevant, the ?p ? display shown above (character pattern no. 1) can be selected by either character code 00h or 07h. 6. when cgram data=?1? the display is turned on. when cgram data=?0? display is turned off.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 18 - march, 2006 dot character vfd controller/driver ic pt6314 timing generation circuit timing signals for internal circuit operations(i .e. ddram, cgram) are generated by the timing generation circuit. the display ram read timing and the mcu access internal operation timing are generated separately in order to avoid interferences. thus, for example, when data is being written to the ddram, no undesirable interference occur (i.e. fli ckering in areas other than the display location) vfd driver circuit the vfd driver circuit is composed of 24 grid and 80 segment signal drivers. during power on, the character font and number of digits are selected by the hardware (ds0 and ds1), the required grid signal drivers automatically output drive waveforms while the other grid signal drivers continue to output non-selected waveforms. the serial data sent is latched when the display data character pattern corresponding to the last address of the display dat a ram (ddram). since the serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, pt6314 drives from the head display. cursor/blink control circuit cursor and character blinking are generated by the curs or / blink control circuit. the cursor or the blinking will appear with the digit located at the display data ram (ddram) address set in the address counter (ac). for example, when the address counter is 08h, the cursor position is displayed at ddram address 08h. ac6 ac5 ac4 ac3 ac2 ac1 ac0 ac 0 0 0 1 0 0 0 for 1-line display: display position digit 1 2 3 4 5 6 7 8 9 10 11 12 ddram address(hexadecimal) 00 01 02 03 04 05 06 07 08 09 0a 0b cursor position for 2-line display: display position digit 1 2 3 4 5 6 7 8 9 10 11 12 00 01 02 03 04 05 06 07 08 09 0a 0b ddram address(hexadecimal) 40 41 42 43 44 45 46 47 48 49 4a 4b cursor position note: the cursor or blinking appears when the address count er (ac) selects the character generator ram (cgram). the cursor and blinking become meaningl ess. when the address counter is a cgram address, the cursor or the blinking is displayed in a meaningless position.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 19 - march, 2006 dot character vfd controller/driver ic pt6314 cpu interface (data transfer) m68 parallel data transfer the m68 type of parallel data transfer is selected when ifsel is set to ?1? and mcu is set to ?0? under this mode, the pt6314 can interface with the cpu in 4 or 8 bits . please take note that the internal registers are composed of 8 bits. during data transfer in 4 bits, db4 to db7 performs the data transfer operation two times, the db0 to db3 mu st be set to either ?h? or ?l?. the higher order 4 bits (d4 to d7) are initially transferred followed by the lower order 4 bits (d0 tod3). please re fer to the diagrams below. 4-bit m68 type parallel data transfer ir7 ir5 ir6 ir4 ir7 ir5 ir6 ir4 ir3 ir1 ir2 ir0 ir3 ir1 ir2 ir0 ir3 ir1 ir2 ir0 d7 d5 d6 d4 d3 d1 d2 d0 bf=0 ir5 ir6 ir4 db7 e r/w rs db6 db5 db4 write instruction read instruction write data write instruction
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 20 - march, 2006 dot character vfd controller/driver ic pt6314 8-bit m68 type parallel data transfer ir7 ir7 bf="0" d7 ir6 ir6 ir6 d6 ir0 ir0 ir0 d0 rs r/w e db7 db6 db0 write instruction write instruction read instruction write data i80 type parallel data transfer the i80 type of parallel data transfer mode is selected when ifsel is set to ?1?and mcu is set to ?0?. a type of pipeline process is performed between lsis vi a the bus holder attached to the internal data bus whenever data is sent from the mcu. it is important to take note that ce rtain restrictions exists in the read sequence of this display data ram. the data of the specified address is not generated by the read instructions issued immediately after the address se tup. this data is generated in the when the data is read the second time. thus, a dummy read is r equired whenever the address setup or write cycle operation is selected. please refer to the diagrams below.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 21 - march, 2006 dot character vfd controller/driver ic pt6314 writing nn+1n+2 n+3 bus holder write signal internal timing latch nn+1n+2 n+3 data /wr mp u reading nn n+1 n+2 column address bus holder internal timing nn n n+1 data /wr mpu preset n increment n+1 n+2 /rd address preset read signal address set #n dummy read data read #n data read #n+1
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 22 - march, 2006 dot character vfd controller/driver ic pt6314 serial data transfer pt6314 supports serial data transfer mode. when data is written, it can be inputted when the strobe goes to ?0?. the first byte -- start byte consists of a total of 8 bits : the synchronous bits (bit 1 - bit 5), r/w (bit 6), rs (bit 7) and bit 8. the register will be selected (ir or dr) by the rs (bit 7) and the data write or read is selected by r/w (bit 6 = ?0?) in th is byte. the start byte is followed by the 8-bit instruction byte. the start byte selects which is process is to be inputted first: read the busy flag + address counter (ac6 to ac0) or read the data wh ich was written in the ddram or cgram. data is outputted at the falling edge of the shift clock. data write 12 3 4 5 678910 11 12 13 14 15 16 "1" "1" "1" "1" "1" r/w rs "0" d7 d6 d5 d4 d3 d2 d1 d0 synchronous bits start byte instruction/data si sck stb data read 12 34 5 678 12 34 5 678 "1" "1" "1" "1" "1" r/w rs "0" ir6 ir5 ir4 ir3 ir2 ir1 ir0 synchronous bits start byte read data si/so sck stb 1s wait time: twait bf "0"
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 23 - march, 2006 dot character vfd controller/driver ic pt6314 instructions instruction rs r/ w db 7 db6 db5 db 4 db 3 db2 db1 db0 description clear display 0 0 0 0 0 0 0 0 0 1 clear all display, and sets ddram address at 00h cursor home 0 0 0 0 0 0 0 0 1 x set ddram address at 00h. also returns the display being shifted to the original position. ddram contents remain unchanged. entry mode set 0 0 0 0 0 0 0 1 1/d s sets the cursor direction and specifies display shift. these operations are performed during the writing/reading of data. display on/off 0 0 0 0 0 0 1 d c b sets all display on/off (d) cursor on/off (c). cursor blinks on character position (b) cursor or display shift 0 0 0 0 0 1 sc r/l x x shifts display or cursor, also keeps ddram contents. function set 0 0 0 0 1 dl n x br1 br0 sets data length (in parallel data transfer) and number of line. cgram address set 0 0 0 1 acg sets address of cgram. after which cgram data is transferred. ddram address set 0 0 1 add sets ddram address, after which ddram data is transferred. read busy flag & address 0 1 bf- =?0? acc reads busy flag (bf) and address counter. bf=?0? write data to cgram or ddram 1 0 write data writes data into the cgram or ddram. read data to cgram or ddram 1 1 read dr data reads data from cgram or ddram notes: 1. i/d=?1?: increment i/d=?0?: decrement 2. s=?1?: display shift enabled s=?0?: cursor shift enabled 3. d, c, b=?1?: turn on d, c, b=?0?: turn off 4. s/c=?1?: display shift s/c=?0?: cursor shift 5. r/l=?1?: shift to the right r/l=?0?: shift to the left 6. dl=?1?: 8 bits dl=?0?: 4 bits 7. n=?0?: 1-line display n=?1?: 2-line display 8. br1, br0=?00?: 100% br1, br0=?10?: 50% br1, br0=?01?: 75% br1, br0=?11?: 25% 9. x=irrelevant 10. ddram: display data ram 11. cgram: character generator ram 12. acg: cgram address 13. add: ddram address 14. acc: address counter
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 24 - march, 2006 dot character vfd controller/driver ic pt6314 ?clear display? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 0 0 0 0 0 0 0 1 during reset, db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 the clear display instruction per forms the following operations: 1. fills all display data ram (ddram) location with 20h (blank character). 2. clears the contents of the address counter (acc) to 00h. 3. sets the display for zero character shift (returns to original position.) 4. sets the address counter to point to the display data ram (ddram). 5. if the cursor is displayed, this instruction will move the cursor to the left most character in the upper display line. 6. sets the address counter (acc) to in crement on each access of the ddram or cgram. ?cursor home? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 0 0 0 0 0 0 1 x the cursor home instruction performs the following operations: 1. clears the contents of the address counter (acc) to 00h. 2. sets the address counter to point to the display data ram (ddram). 3. sets the display for zero character sh ift (returns to the original position). 4. if the cursor is displayed, this instruction moves the cursor to the left most character in the upper line display.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 25 - march, 2006 dot character vfd controller/driver ic pt6314 ?entry mode? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 0 0 0 0 0 1 i/d s the ?i/d? bit provides a way to modify the content s of the address counter after every access to the ddram or cgram. when i/d is set to ?1? the addr ess counter is incremented after the ddram or cgram has been accessed. when the i/d is set to ?0 ? the address counter is decremented after the ddram or cgram has been accessed. the ?s? bit controls the display or cursor shift after each read or write oper ation to the ddram. if s is set to ?1? the ?display shift? instru ction is enabled. if the s is set to ?0 ? the ?cursor shift? instruction is enabled. the direction in which the display is shifted is opposit e to that of the cursor. for example, if s=?0? and i/d=?1? the cursor will shift one character to the ri ght after the mcu writes to the ddram. but, if the s=?1? and i/d=?1? the display will shift one character to the left and the cursor will remain in the same position in the panel display. the cursor has already been shifted in the direction selected by the i/d during the reading of the ddram irrespective of the value of ?s?. reading and writing the cgram always shifts the cursor. both lines are shifted at the same time. the table below shows the various cursor and disp lay shift movements by the ?entry mode set?. i/d s after writing ddram data after reading ddram data 0 0 cursor moves one character to the left. cursor moves one character to the left. 1 0 cursor moves one character to the right . cursor moves one character to the right. 0 1 display shifts one character to the right without any cursor movement. cursor moves one character to the left. 1 1 display shifts one character to the left without any cursor movement. cursor moves one character to the right. during reset, db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 1 0
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 26 - march, 2006 dot character vfd controller/driver ic pt6314 ?display on/off? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 0 0 0 0 1 d c b the above instruction controls the various display features: d=?1?: display on d=?0?: display off c=?1?: cursor on c=?0?: cursor off b=?1?: blinking on b=?0?: blinking off blinking is achieved by alternating a normal and an all ?on? display of a character. the cursor blinks with a frequency of approximately 1 hz and 50% duty. cursor line blink (1hz) during reset, db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 0 ?cursor or display shift? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 0 0 0 1 s/c r/l x x the instruction above will shift the display and/or mo ve the cursor one character to the left or right, without ddram reading or writing. ?s/c? bit selects between the movement of both curs or and display or the movement of the cursor alone. when ?s/c?=?1? the cursor and the display are both shifted. when ?s/c?=?0? only the cursor is shifted. the ?r/l? bit selects the left or right movement dire ction of the cursor and/or display. when ?r/l?=?1? the cursor and/or display is shifted one character to the right. when ?r/l? is ?0? the cursor and/or character is shifted to the left.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 27 - march, 2006 dot character vfd controller/driver ic pt6314 the table below summarizes display and cursor shift and movement. s/c r/l cursor display 0 0 move one character to the left. no shift 0 1 move one character to the right. no shift 1 0 move one character to the left with display shift one character to the left. 1 1 move one character to the right with display shift one character to the right.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 28 - march, 2006 dot character vfd controller/driver ic pt6314 ?function set? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 0 0 1 dl n x br1 br0 the instruction above sets the data length of the data bus lines. this instruction initializes the system, and must be the first instructed executed after power is turned on. the ?dl? and ?n? settings are described below: ?dl?=?1?: 8-bit mcu interface using db7 to db0 ?dl?=?0?: 4-bit mcu interface using db7 to db4 ?n?=?0?: 1-line display using sg1 to sg40. (sg41 to sg80 are fixed at ?low level?) ?n?=?1?:2-line display using sg1 to sg80 x = not relevant br1 and br0 flags are used to modulat e the pulse width of the segment output thereby controlling the vfd brightness. br1 br0 brightness tp 0 0 100% tdsp x 1.00 0 1 75% tdsp x 0.75 1 0 50% tdsp x 0.5 1 1 25% tdsp x 0.25 tdsp P 200 s, tblk P 10 s tp tdsp t tblk tblk sgn g1 gn where n = number of grid, t =n x (tdsp + tblk) during reset, db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 29 - march, 2006 dot character vfd controller/driver ic pt6314 ?cgram address set? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 0 1 a a a a a a the above instruction is used to (1) load new 6-bi t address into the address counter, and (2) set the address counter to point to the cgram. once the ?cgram address set? instructions has been executed, the content s of the address counter (acc) is automatically modified after every acce ss of the cgram, as deter mined by the ?entry mode set? instruction. the active width of the address counter, when it is addressing the cgram is 6 bits. the counter will wrap around from 00h to 3fh if more than 64 bytes of data is written to the cgram. during reset, this instruction is irrelevant. ?ddram address set? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 1 a a a a a a a the above instruction is used to (1) load new 7 bits address into the address counter, and (2) set the address counter to point to the cgram. once the ?ddram address set? instruction has been executed, the contents of the address counter (acc) is automatically modified after every acce ss of the ddram, as determined by the ?entry mode set? instruction. the valid ddram address range is given below. line display number of characters address range 1st line 40 00h to 27h 2nd line 40 40h to 67h during reset, this instruction is irrelevant. ?read busy flag and address? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 bf a a a a a a a the above instruction reads the busy flag (bf) * and the value of the address counter in binary ?aaaaaaa?. this address counter is us ed by the cgram and ddram addresses and its values are determined by the previous instruction. address counter contents are the same as that of ?cgram address set? and ?ddram address set? instructions. note: * the busy flag (bf) = ?0?
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 30 - march, 2006 dot character vfd controller/driver ic pt6314 ?write data to cgram or ddram? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 1 0 d d d d d d d d high order bit low order bit the above instruction write 8 bits bi nary data ?dddddddd? to the cgram or ddram. writing into the cgram or ddram is determined by the previous instruction of the ?cgram or ddram address set?. after a data is written, the va lue of the address is aut omatically increased or decreased by one in accordance to the selection made by the ?entry mode set?. the ?entry mode set? also determines the display shift. ?read data from cgram or ddram? instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 code 1 1 d d d d d d d d high order bit low order bit the above instruction reads the 8 bits binar y data ?dddddddd? from the cgram or ddram. the ?cgram or ddram address set? instruction must be executed first before this instruction can be entered. if the ?cgram or ddram address set? is not executed prior to the ?read data from cgram or ddram? then the first read data becomes invalid. when ?read? instructions are serially executed, the next address data is nor mally read from the second ?read?. before the cursor shifts by the ?cursor or display shift? instruction, the address set instruction do not need to be executed before the read instruction (only applies to ddram). the operati on of the cursor shift instruction is the same as the ?ddram address set? instruction. after reading one data, the value of the address is automatically increased or decreased by 1 in accordance to the selection made in the ?entry mode?. please note that the address counter is automatically increased or decreased by 1 after ?w rite data to cgram or ddram? instruction is executed. at this moment, the address counter?s target data cannot be read if the ?read data from cgram or ddram? instruction is executed. thus, to read data correctly, the ?address set? or ?cursor shift? (if read data from ddram only) inst ruction must be executed before reading.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 31 - march, 2006 dot character vfd controller/driver ic pt6314 power on reset when pt6314 is initialized, the internal status after power supply has been reset is as follows: 1. display clear: 20h (space code) fills the ddram 2. address counter is set to 00h 3. address counter is pointed to the ddram 4. display on/off: d=0, c=0, b=0 (display off) 5. entry mode set: i/d=1, s=0 (increment, cursor shifts are enabled) 6. function set: dl=1, n=1 (8-bit mcu interface, 2-line display are enabled.) 7. brightness control: br0=br1=0 (brightness = 100%) for the mcu interface and duty ratio selection, please refer to the table below. pin name test ifsel ds1 ds0 function remarks 0 x x x self test mode this is effective specially after long usage. 1 0 x x serial interface si/so, sck, stb 1 1 x x parallel interface rs, e, r/w, db7 to db4 or db7 to db0 1 x 0 0 duty=1/16 (16cx1 or 2l display) 1 x 0 1 duty=1/20 (20cx1 or 2l display) 1 x 1 0 duty=1/24 (24cx1 or 2l display) it does not need to use the extension driver. the number of display lines is selected by instruction. 1 x 1 1 duty=1/40 (40cx1 or 2l display) extension driver must be used. the number of display lines is selected by instruction. the above table shows the relationship between t he status of pt6314 and the pin states during reset.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 32 - march, 2006 dot character vfd controller/driver ic pt6314 cgram stroke flowchart set cgram address increment or decrement set cgram address write data to cgram write read data from cgram read ddram stroke flowchart set ddram address increment or decrement set ddram address write data to ddram write read data from ddram read
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 33 - march, 2006 dot character vfd controller/driver ic pt6314 absolute maximum ratings (unless otherwise stated, ta=+25 , vss1=vss2=0v) parameter symbol rating unit logic power supply voltage vdd1 -0.5 to +6.0 v logic input voltage vi -0.5 to vdd1 + 0.5 v logic output voltage vo -0.5 to vdd1 +0.5 v driver power supply voltage vdd2 -0.5 to +60 v driver output voltage vo2 -0.5 to vdd2 + 0.5 v iol2s +10 ma segment ioh2s -4 ma iol2g +10 ma driver output current grid ioh2g -20 ma power dissipation pd 1.2 w operating temperature topr -40 to +85 storage temperature tstg -65 to +150 recommended operating range (unless otherwise specified, ta=+25 , vss1=vss2=0v) parameter symbol min. typ. max. unit logic power supply voltage vdd1 4.5 5.0 5.5 v logic system input voltage vin 0 - vdd1 v driver power supply voltage vdd2 20 - 50 v iol2s - - +5 ma segment ioh2s - - -2 ma iol2g - - +5 ma drive output current grid ioh2g - - -15 ma note: it is recommended that the order in which power is to be applied to the chipset is as follows: vdd1 input vdd2
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 34 - march, 2006 dot character vfd controller/driver ic pt6314 electrical characteristics (unless otherwise specified, ta=-40 to +85 , vdd1=5.0v, vdd2=50v, vss1=vss2=0v) parameter symbol condition min. typ. max. unit high level input voltage 1 vih1 logic, expect e/sck,reset 0.7vdd1 - - v low level input voltage 1 vil1 logic, expect e/sck,reset, dls - - 0.3 vdd1 v high level input voltage 2 vih2 e/sck, reset 0.8vdd1 - - v low level input voltage 2 vil2 e/sck, reset,dls - - 0.2 vdd1 v high level output voltage (logic) voh1 dbn, si/so, sdo, slk, latch,/clr, ioh1=-0.1ma vdd1-0.5 - - v low level output voltage (logic) vol1 dbn, si/so, sdo, slk, latch,/clr, iol1=+0.1ma - - vss1+0.5 v high level input current iih test, vin=vdd1 20 - 500 a high level leakage current iloh logic, vinout=vdd1 - - 1.0 a low level leakage current ilol logic, vinout=vss1 - - -1.0 a voh2s1 sg1to sg80, ioh2=-1ma 46 - - v voh2s2 sg1 to sg80, ioh2=-2ma 45 - - v high level output voltage (driver) voh2g gr1 to gr24, iol2=-15ma 45 - - v low level output voltage (driver) vol2 sg1 to sg80, gr1 to gr24 iol2=1ma - - 5 v idd1 logic - - 100 a current consumption idd2 driver - - 100 a note: the typical (typ.) value is a reference value when ta=25 . switching characteristics (unless otherwise specified, ta=-40 to +85 , vdd1=5.0 10%) parameter symbol condition min. typ. max. unit oscillation frequency fosc r=56k ? 392 560 728 khz operation frequency fc osc1 external clock 450 560 900 khz rise time ttlh1 sg1 to sg80, cl=50pf - - 1.0 s rise time (see note 2) ttlh2 gr1 to gr24, cl=50pf - - 1.0 s fall time tthl sg1 to sg80, gr1 to gr24 cl=50pf - - 1.0 s
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 35 - march, 2006 dot character vfd controller/driver ic pt6314 switching timing tthl 90% 10% 90% 10% ttlh1, 2 sgn, grn timing 1 requirements (unless otherwise specified, ta=-40 to +85 ) m68 interface parallel data transfer: write (vdd1=5.0v 10%) parameter symbol condition min. typ. max. unit enable cycle time tcyce e e 500 - - ns enable ?h? pulse width pweh e 230 - - ns enable ?l? pulse width pwel e 230 - - ns rs, r/w - e setup time tas rs,r/w e 20 - - ns rs, r/w - e hold time tah e rs,r/w 10 - - ns data setup time tds data e 80 - - ns data hold time tdh e data 10 - - ns reset pulse width twre 500 - - ns m68 interface parallel data transfer: read (vdd1=5.0 10%) parameter symbol condition min. typ. max. unit enable cycle time tcyce e e 500 - - ns enable ?h? pulse width pweh e 230 - - ns enable ?l? pulse width pwel e 230 - - ns rs, r/w - e setup time tas rs,r/w e 20 - - ns rs, r/w - e hold time tah e rs,r/w 10 - - ns data delay time tdd e data - - 160 ns data hold time tdhr e data 5 - - ns
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 36 - march, 2006 dot character vfd controller/driver ic pt6314 parallel i/f (m68 input) tas tah pw eh pw el rs r/w /c s e td s td h valid data tcyce db0 to db7 parallel i/f (m68 output) tas tah pw e pw e rs r/w /c s e td d td h r valid data tcyce db0 to db7 notes: 1. input signal rise time and fall time (tf, tr) < 15ns. 2. all timing is specified using 0.20vdd1 and 0.80vdd1 as reference. 3. pweh is the overlap between /cs=?l? and e.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 37 - march, 2006 dot character vfd controller/driver ic pt6314 timing 2 requirements (unless otherwise specified, ta=-40 to +85 ) i80 interface parallel data transfer: write (vdd1=5.0 10%) parameter symbol condition min. typ. max. unit rs hold time trh8 10 - - ns rs setup time trs8 10 - - ns system cycle time tcyc8 168 - - ns control ?l? pulse width (wr) tcclw /wr 30 - - ns control ?l? pulse width (rd) tcclr /rd 70 - - ns control ?h? pulse width (rd) tcchw /wr 100 - - ns control ?h? pulse width (rd) tcchr /rd 70 - - ns data setup time tds8 d0 to d7 55 - - ns data hold time tdh8 do to d7 55 - - ns rd access time tacc8 do to d7, cl=100pf - - 70 ns output disable time toh8 do to d7, cl=100pf 5 - - ns reset pulse width twre 500 - - ns parallel i/f (i80) tr tr trh s tcclr, tcclw tcyc s to ss tac c s to hs to hs tcchr, tcchw tr rs /cs /w r, /rd d 0 to d7 (write) d 0 to d7 (read) tr s8 notes: 1. input signal rise time and fall time (tf, tr) < 15ns 2. all timing is specified using 0.20vdd1 and 0.80vdd1 as reference. 3. tcclw and tcclr are specified as t he overlap between /cs=?l? /wr and /rd=?l?
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 38 - march, 2006 dot character vfd controller/driver ic pt6314 timing 3 requirements (unless otherwise specified, ta=-40 to +85 ) serial data transfer: (vdd1=5v 10%) parameter symbol condition min. typ. max. unit shift clock cycle tcyk sck 500 - - ns high level shift clock pulse width twhk sck 200 - - ns low level shift clock pulse width twlk sck 200 - - ns shift clock hold time thstbk stb sck 100 - - ns data setup time tds data sck 100 - - ns data hold time tdh sck data 100 - - ns stb hold time tdkstb sck stb 500 - - ns stb pulse width twstb 500 - - ns wait time twait 8th clk 1st clk 1 - - ns output data delay time todd sck data - - 150 ns output data hold time todh sck data 5 - - ns reset pulse width twre 500 - - ns serial i/f (input) thstbk tcyk twhk twlk stb sck si twstb tckstb tds tdh
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 39 - march, 2006 dot character vfd controller/driver ic pt6314 serial i/f (output) thstbk tcyk twhk twlk stb sck so twstb tdkstb todd todh notes: 1. input signal rise time and fall time (tf, tr) < 15 ns. 2. all timing is specified using 0.20vdd1 and 0.80vdd1 as reference. ac measurement point vih vil voh vol inpu t output reset /reset tw re
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 40 - march, 2006 dot character vfd controller/driver ic pt6314 timing 4 requirements (unless otherwise specified, ta=-40 to +85 ) m68 & i80 serial interface common timing: power on reset (vdd1=5.0 10%) parameter symbol condition min. typ. max. unit reset time tres vdd 100 - - s vdd rising time trdd vdd 1 - - s vdd off width toff vdd 1 - - ms toff 0.2v 4.5v trdd tres internal reset time vdd
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 41 - march, 2006 dot character vfd controller/driver ic pt6314 english/japanese character font table (pt6314-001)
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 42 - march, 2006 dot character vfd controller/driver ic pt6314 english/european character font table (pt6314-002)
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 43 - march, 2006 dot character vfd controller/driver ic pt6314 special character font table (PT6314-16)
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 44 - march, 2006 dot character vfd controller/driver ic pt6314 application circuit 1: serial interface sg2 39 sg3 40 gr2 gr3 gr24 15 14 13 27 28 29 rl1 rl2 /clr stb sck si/so mcu 50v 1 36 34 35 3 5 67910 11 24 5v 5v 5 x 8 dot x 24grid x 2 line vfd pt6314 56k vdd2 vdd2 vss1 vss1 vss2 vdd1 osc2 /reset dls ds1 ds0 ifset osc1 143 gr1 142 gr2 141 gr3 120 gr2 4 143 142 141 120 119 39 38 sg79 118 sg80 119
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 45 - march, 2006 dot character vfd controller/driver ic pt6314 application circuit 2: i80 interface sg2 39 sg3 40 gr2 gr3 gr24 12 13 14 27 28 29 rl1 rl2 /clr /rd rs /wr mcu 50v 1 36 34 35 3 5 67910 11 24 5v 5v 5 x 8 dot x 24grid x 2 line vfd pt6314 56k vdd2 vdd2 vss1 vss1 vss2 vdd1 osc2 /reset dls ds1 ds0 ifset osc1 143 gr1 142 gr2 141 gr3 120 gr2 4 143 142 141 120 119 39 38 sg79 118 sg80 119 25 mpu 16 db0 23 db7
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 46 - march, 2006 dot character vfd controller/driver ic pt6314 application circuit 3: m68 interface sg2 39 sg3 40 gr2 gr3 gr24 12 13 14 27 28 29 rl1 rl2 /clr e rs r/w mcu 50v 1 36 34 35 3 5 67910 11 24 5v 5v 5 x 8 dot x 24grid x 2 line vfd pt6314 56k vdd2 vdd2 vss1 vss1 vss2 vdd1 osc2 /reset dls ds1 ds0 ifset osc1 143 gr1 142 gr2 141 gr3 120 gr2 4 143 142 141 120 119 39 38 sg79 118 sg80 119 25 mpu 16 db0 23 db7
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 47 - march, 2006 dot character vfd controller/driver ic pt6314 ordering information order part number package type top code pt6314-001 144 pins, lqfp pt6314-001 pt6314-002 144 pins, lqfp pt6314-002 PT6314-16 144 pins, lqfp PT6314-16 pt6314-001 (l) 144 pins, lqfp pt6314-001 pt6314-002 (l) 144 pins, lqfp pt6314-002 PT6314-16 (l) 144 pins, lqfp PT6314-16 notes: 1. (l), (c) or (s) =lead free. 2. the lead free mark is put in front of the date code.
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 48 - march, 2006 dot character vfd controller/driver ic pt6314 package information 144 pins, lqfp (body size: 20 x 20mm, pitch size: 0.50mm, thk body: 1.40mm) 1 2 3 sl 0.25mm gauge plane r2 r1 -d- d1 d e1 e -a- -b- -h- e b a2 a 1 a c l1 c seating plane ccc c
tel: 886-2-66296288 fax: 886-2-29174598 url: http://www.princeton.com.tw pt6314 v1.3 - 49 - march, 2006 dot character vfd controller/driver ic pt6314 symbol min. nom. max. a - - 1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 d 22.00 bsc. d1 20.00 bsc. e 0.50 bsc. e 22.00 bsc. e1 20.00 bsc. 0 o 3.5 o 7 o 1 0 o - - 2 11 o 12 o 13 o 3 11 o 12 o 13 o c 0.09 - 0.20 l 0.45 0.60 0.75 l1 1.00 ref. r1 0.08 - - r2 0.08 - 0.20 s 0.20 - - ccc 0.08 notes: 1. controlling dimensions are in millimeters. 2. dimensioning and toleranc ing per asme y14.5m-1994. 3. the top packge body size may be smaller than the bottom package size by as much as 0.15mm. 4. datums a-b and d to be determined at datum plane h. 5. dimensions d1 and e1 do not in clude mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body si ze dimensions including mold mismatch. 6. details of pin1 identifier are optional but must be located within the zone indicated. 7. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead to exceed the maximum b dimension by more than 0.08mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. 8. a1 is defined as the distance from the seat ing plane to the lowest point on the package body. 9. refer to jedec std ms-026 variation bfb jedec is the trademark of jedec so lid state technology association

▲Up To Search▲

Price & Availability of PT6314-16

	To Download PT6314-16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .